1. Field of the Invention
This invention relates to a plating technology. More particularly, the invention relates to a method, and an apparatus, for controlling plating so as not to create variance in plating areas when a pattern-providing plating film is formed at a predetermined film thickness on a substrate, a control program and a recording medium that are used for such a control method and apparatus, and a plating method. As the invention can exactly control the plating area, based on such an exactly controlled plating area, the invention can appropriately assist a design change, such as feedback of design change to a designing department of patterns, and preconsideration of production conditions. Therefore, the invention can be used advantageously for producing printed wiring boards, in particular.
2. Description of the Related Art
Generally speaking, a printed wiring board is produced through a series of steps of boring holes in a substrate comprising a copper-clad laminate board, sequentially applying electroless copper plating and electrolytic copper plating to form a conductor layer having a predetermined thickness on the entire surface of the board, and selectively etching away unnecessary portions of the conductor layer to form wiring or the like in a desired pattern. Because remarkable progress has been made in recent years in the higher density of printed wiring boards and their multi-layered construction and a higher operational speed of devices mounted onto the boards, improvement in and management of plating steps have become very important. For example, it has been desired to provide a plating method capable of easily coping with production of a variety of kinds of products in limited quantities and with frequent design changes. If plating areas have any variance, the plating thickness becomes small or large, so that electrical characteristics are deteriorated and a waste of materials occurs. Therefore, strict management of the plating steps inclusive of the plating area has become necessary.
Japanese Unexamined Patent Publication (Kokai) No. 56-64493, for example, discloses a production method, for a printed board, which uses a photo-mask to correct a circuit pattern width to cope with variance in the thickness of electric copper plating in an etching step carried out after chemical copper plating and electric copper plating in order to minimize variance in the copper plating thickness. Japanese Unexamined Patent Publication (Kokai) No. 1-321308, now U.S. Pat. No. 2,593,690, discloses a plating area measurement apparatus for a printed wiring board characterized in that means, for calculating a pattern area from given pattern data and means for calculating an inner area of each through-hole from boring data and sheet thickness data, calculate a plating area of a printed wiring board so as to omit an expensive and troublesome step that uses a negative film for an optical measuring instrument, when the plating area is measured, to keep the plating thickness constant. Further, Japanese Unexamined Patent Publication (Kokai) No. 2001-123298 discloses an electrolytic plating method that determines in advance a relational formula between an electrode potential and a current density and determines, on the other hand, a current value and a potential value when a plating object is polarized in a plating bath, calculates a plating area of a plating object from the relational formula, the current value and the potential value and conducts plating to a predetermined thickness, so as to reduce a variance in a deposition film thickness of a plating metal.
As described above, attempts have already been made to measure and control variance of the plating area to solve the problem of variance of the thickness of the plating film formed on the substrate for forming the pattern in the production of the printed wiring board according to the prior art. However, the prior art plating methods have employed only a method that optically scans the whole surface of one of the surface of the substrate and measures the plating area of the substrate as a whole. Therefore, this method cannot measure and adjust variance of the plating areas between top and back surfaces of the substrate. Thus, this method cannot sufficiently satisfy the recent technical progresses and requirements described above for the following reasons. If the plating area is different between a certain plating region and another when a plating film is considered as a single surface (single body) of the substrate, variance occurs in the plating thickness (when an additive method is used) or in an etching amount (when a subtractive method is used). Further, problems of planarity and warping of the substrate occur. When an insulating film is formed on or below the plating film, control of the film thickness of the insulating film becomes difficult, and insulating defects and connection defects occur due to a flow of the insulating resin.